1. Field of the Invention
This invention relates to integrated circuits and, in particular, to the provision of power and ground planes in an integrated circuit package.
2. Related Art
The presence of resistance, capacitance and inductance in the electrical conductors (e.g., bond wires, leads) within an integrated circuit package gives rise to noise (signal delays and signal distortions) in the electrical signals transmitted to and from the integrated circuit (a semiconductor die on which electrically conductive circuitry and bond pads are formed). Two sources of noise in an integrated circuit package are switching noise (.DELTA.I noise) and crosscoupling noise (crosstalk). Switching noise may be an inductive voltage spike that occurs on a conductive path as the result of rapid current switching in the conductive path. Crosstalk is the undesirable appearance of an electrical current in a conductive path as a result of mutual capacitance and inductance between the conductive and other nearby conductive paths.
By varying the geometries and materials of integrated circuit package components such as signal leads, bond wires, vias, ground planes and power planes, various electrical characteristics of the integrated circuit package can be changed such as decoupling capacitances, resistances and self-inductances of current paths, and capacitances and mutual inductances between adjacent current paths. As a consequence, electrical noise can be reduced.
In current high speed digital systems, subnanosecond signal transition times are common. Such high speed operation exacerbates the problems of switching noise and crosstalk. Bond wire inductance, effective inductance in power, ground and signal (i.e., other than power or ground) paths, and inductive coupling between adjacent current paths are particularly troublesome.
Previously, ground and power planes have been used in integrated circuit packages in an attempt to provide uniform ground and power supplies to the integrated circuit and to reduce electrical noise. FIG. 1 is a cross-sectional view of a typical packaged integrated circuit 100 comprising a semiconductor die 101 attached with an adhesive 102 to an electrically conductive die attach pad 103 on which is formed a ground plane or power plane. Electrically conductive leads 104 are attached to the die attach pad 103 with electrically insulative adhesive 105. Layer 106, which comprises a ground or power plane, is attached to the die attach pad 103 with an electrically insulative adhesive 107 on a side of the die attach pad 103 opposite that to which the die 101 is attached. Bond wires 108 are used to make electrical connection between selected ones of the leads 104, the die attach pad 103, and the die 101.
Such a multilayer structure has several disadvantages. Conductive vias and traces are often necessary as part of the connection from the power and/or ground plane to on-chip supply or ground. These vias and traces have an additional self-inductance that increases switching noise. Additionally, the multilayer structure is more complex and expensive to produce since additional metal layers, dielectric layers, traces and vias must be formed. This additional complexity can adversely affect the electrical and mechanical reliability of the integrated circuit package.
It is desirable to increase the cross-sectional area and minimize the length of current paths so as to minimize the self-inductance of current paths (especially power and ground paths). Thus, there is a need for an integrated circuit package in which the above benefits are achieved and the above problems overcome.